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FAST CMOS BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
IDT54/74FCT810BT/CT
FEATURES:
* * * * * * * * 0.5 MICRON CMOS technology Guaranteed low skew < 600ps (max.) Very low duty cycle distortion < 700ps (max.) Low CMOS power levels TTL compatible inputs and outputs TTL level output voltage swings High drive: -32mA IOH, 48mA IOL Two independent output banks with 3-state control - One 1:5 Inverting bank - One 1:5 Non-Inverting bank * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages * Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ noninverting clock driver built using advanced dual metal CMOS technology. It consists of two banks of drivers, one inverting and one non-inverting. Each bank drives five output buffers from a standard TTL-compatible input. The IDT54/ 74FCT810BT/CT have low output skew, pulse skew and package skew. Inputs are designed with hysteresis circuitry for improved noise immunity. The outputs are designed with TTL output levels and controlled edge rates to reduce signal noise. The part has multiple grounds, minimizing the effects of ground inductance.
FUNCTIONAL BLOCK DIAGRAMS
PIN CONFIGURATIONS
VCC 1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 20 19 18 17 16 15 14 13 12 11 VCC OB1 OB2 OB3 GND OB4 OB5 GND OEB INB
3103 drw 02
OEA 5 INA OA1-OA5
OA1 OA2 OA3 GND
OEB 5 INB OB1-OB5
3103 drw 01
OA4 OA5 GND OEA INA
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
OA2 OA1
INDEX
3 OA3 GND OA4 OA5 GND 4 5 6 7 8
2
1
20 19 18 17 OB2 OB3 GND OB4 OB5
L20-2
OB1
16 15 14
9 10 11 12 13
OEA
VCC INB
OEB
INA
VCC
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC TOP VIEW
GND
3103 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
OCTOBER 1995
DSC-4646/3
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IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current Commercial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
OEA, OEB
INA, INB OAn, OBn
Pin Names
Description 3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs
3103 tbl 01
-0.5 to VCC +0.5 0 to +70 -55 to +125 -55 to +125 -60 to +120
-0.5 to VCC +0.5 -55 to +125 -65 to +135 -65 to +150 -60 to +120
V C C C mA
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. Unit 6.0 pF 8.0
pF
3103 lnk 02
NOTE: 1. This parameter is measured at characterization but not tested.
3103 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals. 3. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL II VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current (5) Input LOW Current (5) High Impedance Output Current (3-State Output pins) (5) Input HIGH Current (5) Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Min., IIN= -18mA VCC = Max.(3) , VO = GND IOH = -12mA MIL. IOH = -15mA COM'L. IOH = -24mA MIL. IOH = -32mA COM'L.(4) VCC = Min. IOL = 32mA MIL. VIN = VIH or VIL IOL = 48mA COM'L. VCC = 0V, VIN or VO 4.5V -- VCC = Max., VIN = GND or VCC VCC = Min. VIN = VIH or VIL Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V VCC = Max., VI = VCC (Max.) Min. 2.0 -- -- -- -- -- -- -- -60 2.4 2.0 -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 -120 3.3 3.0 0.3 -- 150 5 Max. -- 0.8 1 1 1 1 1 -1.2 -225 -- -- 0.55 1 -- 500 V A mV A Unit V V A A A A A V mA V
VOL
IOFF VH
Output LOW Voltage Input/Output Power Off Leakage(5) Input Hysteresis for all inputs Quiescent Power Supply Current
ICCL ICCH ICCZ
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
3103 lnk 04
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IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OEA = OEB = GND 50% Duty Cycle VCC = Max. Outputs Open fo= 25MHz 50% Duty Cycle OEA = GND, OEB =VCC VCC = Max. Outputs Open fo = 50MHz 50% Duty Cycle OEA = OEB = GND VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 60 Max. 2.0 100 Unit mA A/ MHz/bit
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
7.5
13
mA
-- --
7.8 30.0
14.0 50.5 (5)
--
30.5
52.5 (5)
3103 tbl 05
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO= Output Frequency NO= Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz.
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IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT54/74FCT810BT Com'l. Symbol Parameter tPLH Propagation Delay INA to OAn, INB to OBn tPHL tR Output Rise Time tF Output Fall Time tSK1(o) Output skew (same bank): skew between outputs of same bank and same package (same transition) tSK2(o) Output skew (all banks): skew between outputs of all banks of same package (inputs tied together) tSK(p) tSK(t) Pulse skew: skew between opposite transitions of same output |(tPHL-tPLH)| Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn Output Disable Time OEA to OAn, OEB to OBn Condition(1) CL = 50pF RL = 500
Min.(2)
IDT54/74FCT810CT Com'l.
Max.
Mil. 1.5 -- -- -- 4.9 2.0 1.5 0.9
Mil.
Min. (2) Max.
Max. Min.(2)
Max. Min.(2)
1.5 -- -- --
4.5 1.5 1.5 0.5
1.5 -- -- --
4.3 1.5 1.5 0.3
1.5 -- -- --
4.6 2.0 1.5 0.7
Unit ns ns ns ns
--
0.7
--
1.1
--
0.6
--
1.0
ns
-- --
0.7 1.2
-- --
1.2 1.5
-- --
0.7 1.0
-- --
1.1 1.2
ns ns
tPZL tPZH tPLZ tPHZ
1.5 1.5
6.0 6.0
1.5 1.5
6.5 6.5
1.5 1.5
5.0 5.0
1.5 1.5
6.0 6.0
ns ns
3103 tbl 06 NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
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IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUIT FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL
3103 drw 04
ENABLE AND DISABLE TIME SWITCH POSITION
7.0V
V OUT
Test Disable LOW Enable LOW Disable HIGH Enable HIGH
Switch Closed Open
500
3103 lnk 07 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
TEST WAVEFORMS PACKAGE DELAY
3V 1.5V INPUT tPLH tPHL 2.0V OUTPUT tR tF
3103 drw 05
OUTPUT SKEW (SAME BANK) - tSK1(o)
INPUT tPLH1 tPHL1 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL
0V VOH 1.5V 0.8V VOL OUTPUT 2 OUTPUT 1
tSK1(o)
tSK1(o)
tPLH2
tPHL2
3103 drw 06
tSK1(o) = |tPLH2 - tPLH1| or |tPHL2 - tPLH1|
OUTPUT SKEW (ALL BANKS) - tSK2(o)
INPUT 3V 1.5V 0V VOH 1.5V VOL tSK2(o) OUTPUT 2 tPHL2 tPLH2
3103 drw 07
PULSE SKEW - tSK(p)
INPUT tPLH tPHL 3V 1.5V 0V VOH 1.5V VOL tSK(p) = |tPHL - tPLH|
3103 drw 08
tPLH1
tPHL1
OUTPUT 1 tSK2(o)
VOH 1.5V VOL
OUTPUT
tSK2(o) = |tPHL2 - tPLH1| or |tPLH2 - tPHL1|
PACKAGE SKEW - tSK(t)
INPUT tPD1a 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL tPD2a tPD2b
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V 0.3V t PHZ 0.3V VOH 0V
3103 drw 10
DISABLE 3V 1.5V 0V t PLZ 3.5V VOL
tPD1b
PACKAGE 1 OUTPUT tSK2(o) PACKAGE 2 OUTPUT tSK2(o)
tSK(t) = |tPD2a - tPD1a| or |tPD2b- tPD1b|
Package 1 and Package 2 are same device type and speed grade 3103 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns 9.4
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IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXXFCT Temp. Range XXX Device Type XX Package X Process/ Temperature Range Blank B Commercial Military (-55C to +125C) Compliant to MIL-STD-883, Class B Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline IC Quarter-size Small Outline IC Inverting, Non-Inverting Buffer/Clock driver
P D E L SO PY Q 810BT 810CT 54 74
-55C to +125C 0C to + 70C
3103 drw 13
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